Recently, as wired/wireless broadcasting and telecommunication-related technologies and services have been rapidly developed, and thus the level of users' demand for products has been increasing, advanced information communication equipment and systems are being equipped with various functions and becoming smaller in size so as to be easily carried. To implement this, high-speed digital systems are becoming faster and wider in bandwidth. As the clock frequency falls within the range of several GHz with such increase in the operating speed of the advanced equipment and systems, the problem of signal/power integrity and electromagnetic interference, which is caused by simultaneous switching noise (SSN) generated in a multilayer package or in a multilayer PCB structure, is considered as one of the most important issues in designing the chip/package and PCB of a high-speed system.
First, the multilayer PCB and package structure will be described. In the multilayer PCB and package structure, generally, a power plane and a ground plane constituting a power distribution network (PDN) are paired and placed inside the multilayer structure, which form a parallel plate waveguide configuration. Shown in FIG. 1 is a mechanism in which noise is generated in a PDN including power and ground planes due to layer arrangement, signal flow, and a high-speed switching device, such as an IC chip, in a multilayer PCB and package structure using a high-speed signal.
FIG. 1 is a view showing a signal flow and noise generation mechanism in a multilayer PCB and package structure using a high-speed signal.
Referring to FIG. 1, simultaneous switching noise (SSN) 102 is known to be the most serious noise in a multilayer PCB and chip/package structure. The SSN 102, also referred to as Delta-I noise or ground bounce noise (GBN), is generated by time-varying currents that change fast in a high-speed digital circuit. The SSN 102 generated between the power plane and a ground plane affects the signal/power integrity of the circuits and also causes unwanted electromagnetic interference (EMI) 104 to be radiated from the edges of a PCB board. Thus, the SSN 102 is becoming an important issue in high-speed digital systems operating at a low voltage level at a high-speed clock frequency.
A recent high-speed digital system has several hundreds of input/output gates for simultaneous switching. If a fast current flows through vias in the multilayer PCB/package due to simultaneous switching of the large number of gates, unwanted noise (SSN 102) is generated between the power plane and ground plane as shown in FIG. 1, and the generated SSN 102 is propagated across the PCB/package by a resonance mode of a parallel conducting plate and then unwanted EMI 104 is radiated from the edges of the PCB/package. That is, the SSN 102 is inductive noise generated when many output terminals of the digital circuit simultaneously switch. Since the amount of the SSN 102 depends on the configuration and current path of the PCB/package, it is difficult to measure a precise amount of the noise. However, the noise can be represented most simply by the following equation:
                              V          noise                =                              N            ·                          L              eq                                ⁢                                    ⅆ              i                                      ⅆ              t                                                          Equation        ⁢                                  ⁢                  (          1          )                    
wherein Vnoise is a noise voltage, N is the number of simultaneously switching gates, and Leq is an inductance value caused by current flowing through each driver during simultaneous switching.
So far, one of the most typical methods to solve the problem of signal/power integrity or EMI generated by SSN in analog and digital systems is to mount a device having a large capacitance, which is called a decoupling capacitor (DeCap), between the power layer and the ground layer. Research for eliminating a parasitic inductance component of the power distribution network (PDN) and properly supplying power to an integrated circuit device by the decoupling capacitor has been continuously conducted. However, the mounting of the DeCap on the PCB increases production costs, and also occupies the space of the PCB board, thus making the placement of various devices restrictive. Also, the parasitic inductance component of the DeCap may cause another parallel resonance frequency. Due to the parasitic inductance, the DeCap can operate only up to several hundreds of MHz, and thus the SSN having a GHz frequency component, which has become a problem in recent high-speed digital systems, cannot be eliminated.
The most frequently used method in efforts to reduce the parasitic inductance component of the DeCap is an embedded thin film capacitor that has a thin film material having a high dielectric constant disposed between power and ground planes. The use of the embedded thin film capacitor makes SSN reduction characteristic improve even in a higher frequency band than that of the DeCap. However, the embedded thin film capacitor also has a limited frequency band of several hundreds of MHz for use, and in order to put the embedded thin film capacitor to practical use, additional research on the composition of a material having a high dielectric constant and processing techniques using the same is required.
Besides, various methods, such as stitching vias, ground filling, and the like, have been proposed, but most of the methods are disadvantageous in that they operate locally in limited areas rather than across the substrate and show SSN suppression characteristics only in a narrow frequency band less than GHz, and thus it is known their effects are known to be insignificant in the current high-speed systems.
Meanwhile, new methods for solving the problems caused by SSN in a GHz band are being studied, and research is ongoing to reduce EMI by eliminating SSN in a chip/package and multilayer PCB structure and thus improving power integrity/signal integrity (PI/SI), by using an electromagnetic bandgap (EBG) structure highly applicable as an EMI reduction technique in a GHz band, that is, an EBG structure having a high impedance characteristic in a specific frequency band to provide a wide bandgap characteristic for currents flowing on surfaces. Reducing SSN by using an EBG in the multilayer PCB/package structure allows more effective PI/SI reduction and EMI suppression than using a DeCap or embedded thin film capacitor, and shows more excellent characteristics in selecting a frequency band to be suppressed.
However, a mushroom-type EBG structure formed in a double-layer structure has disadvantages that it is difficult to manufacture blind vias and the like in terms of process steps and additional costs are required. To overcome this problem, there has been suggested a single-plane EBG structure using periodic structure of an appropriate pattern on a ground plane or power plane. Although this structure can attain considerable noise reduction in a power distribution network (PDN) having a parallel plate waveguide configuration, it is disadvantageous in that it affects high-speed signals flowing over the ground/power planes to which the EBG structure is applied, and there is a limitation on the lowest frequency of a frequency band to be suppressed. Moreover, in case where an EBG structure is provided only on the ground plane or power plane, self-impedance at the region where the EBG structure is placed, especially in a low frequency band, increases, and thus the generation of unwanted electromagnetic waves becomes more dominant.